185 lines
3.7 KiB
ArmAsm
185 lines
3.7 KiB
ArmAsm
# Multiboot2 header and x86_64 long-mode bootstrap
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.section .multiboot2, "a"
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.align 8
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multiboot_header:
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.long 0xe85250d6
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.long 0
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.long multiboot_header_end - multiboot_header
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.long -(0xe85250d6 + 0 + (multiboot_header_end - multiboot_header))
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/* Framebuffer tag: type=5, size=20, width=height=0 (any), depth=32.
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* Layout per multiboot2 spec:
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* u16 type, u16 flags, u32 size, u32 width, u32 height, u32 depth
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* Padded to 8-byte alignment. */
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.align 8
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.word 5
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.word 0
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.long 20
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.long 0
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.long 0
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.long 32
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.long 0 /* padding to 8-byte alignment */
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.align 8
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.word 0
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.word 0
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.long 8
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multiboot_header_end:
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.section .bss, "aw", @nobits
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.align 4096
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pml4:
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.space 4096
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pdpt:
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.space 4096
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pd:
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.space 4096 * 4
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.align 16
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stack_bottom:
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.space 16384
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stack_top:
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.align 8
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mboot_info_ptr:
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.space 8
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.section .text
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.code32
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.global _start
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.type _start, @function
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_start:
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movl $stack_top, %esp
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movl %ebx, mboot_info_ptr
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cld
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movl $__bss_start, %edi
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movl $__bss_end, %ecx
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subl %edi, %ecx
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xorl %eax, %eax
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rep stosb
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movl $pdpt, %eax
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orl $0x03, %eax
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movl %eax, pml4
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/* Populate 4 PDPT entries, each pointing to one of 4 PDs.
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* This identity-maps the first 4 GiB using 2 MiB pages,
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* which covers typical framebuffer/MMIO regions. */
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movl $pd, %eax
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orl $0x03, %eax
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movl %eax, pdpt + 0
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addl $4096, %eax
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movl %eax, pdpt + 8
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addl $4096, %eax
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movl %eax, pdpt + 16
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addl $4096, %eax
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movl %eax, pdpt + 24
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movl $0x00000083, %eax
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movl $pd, %edi
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movl $2048, %ecx
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1:
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movl %eax, (%edi)
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addl $0x200000, %eax
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addl $8, %edi
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loop 1b
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movl $pml4, %eax
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movl %eax, %cr3
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movl %cr4, %eax
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orl $0x20, %eax
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movl %eax, %cr4
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movl $0xC0000080, %ecx
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rdmsr
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orl $0x100, %eax
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wrmsr
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movl %cr0, %eax
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orl $0x80000000, %eax
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movl %eax, %cr0
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lgdt gdt64_pointer
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ljmp $0x08, $long_mode_start
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.code64
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long_mode_start:
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/* Load data segment registers with the data descriptor (0x10).
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* In long mode most of these are ignored for access checks, but
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* %ss must be a valid (or null) selector so that iretq from an
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* interrupt can safely reload it. */
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movw $0x10, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %fs
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movw %ax, %gs
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movw %ax, %ss
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movabsq $stack_top, %rax
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movq %rax, %rsp
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/* Ensure 16-byte alignment for the System V AMD64 ABI. */
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andq $-16, %rsp
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movq mboot_info_ptr, %rdi
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call kernel_main
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cli
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1:
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hlt
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jmp 1b
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.code64
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.global isr_keyboard
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.align 16
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isr_keyboard:
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/* Save all caller-saved registers used by the SysV AMD64 ABI. */
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pushq %rax
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pushq %rcx
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pushq %rdx
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pushq %rsi
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pushq %rdi
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pushq %r8
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pushq %r9
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pushq %r10
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pushq %r11
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/* On interrupt entry the CPU pushed 5 qwords (40 bytes), and we
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* pushed 9 more (72 bytes) = 112 bytes total. That leaves %rsp
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* misaligned by 8 relative to a 16-byte boundary after the
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* upcoming `call`. Push one dummy qword to realign. */
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subq $8, %rsp
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cld
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call keyboard_handler
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addq $8, %rsp
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popq %r11
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popq %r10
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popq %r9
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popq %r8
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popq %rdi
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popq %rsi
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popq %rdx
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popq %rcx
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popq %rax
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iretq
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.section .note.Xen, "a", @note
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.align 4
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.long 4
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.long 4
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.long 18
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.asciz "Xen"
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.align 4
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.long _start
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.section .rodata
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.align 8
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gdt64:
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.quad 0x0000000000000000 /* 0x00: null descriptor */
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.quad 0x00209A0000000000 /* 0x08: 64-bit code, DPL=0 */
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.quad 0x0000920000000000 /* 0x10: data, writable, present */
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gdt64_end:
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gdt64_pointer:
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.word gdt64_end - gdt64 - 1
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.quad gdt64
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